`timescale 1 ns / 1 ps
/*------------------- include --------------------*/

/*---------------------------------------------*/

`define SYS_FREQ 8_000_000 
module tb; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000.0/(`SYS_FREQ/1000000.0); 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

/*---------------------------- mcu nets --------------------------*/


/*----------------------------- 模块 ------------------------------*/

wire [7:0] o_port , o_portid ;
wire o_wen ;

meu #(
    .ROM_FILE ("firmware.hex"),
    .ROM_NUM (256),
    .RAM_SIZE ( 256)
) u_eu (
    .clk(clk),
    .rst_n(rst_n),

    .o_wen(o_wen),
    .o_portid(o_portid),
    .o_port(o_port),
    .i_port()
);


always @(posedge clk ) begin
    if(o_wen) begin
        $display("%f ms %d ns Output @0x%02x:0x%02x",$time/1000000.0 , $time , o_portid, o_port) ;
        // if(o_portid == 8'hff)
        //     $write("%c",o_port) ;
        // else
        //     $display("%f ms %d ns Output @0x%02x:0x%02x",$time/1000000.0 , $time , o_portid, o_port) ;
    end
end


initial begin
    $display(" -------- meu sim ----------");
    rst_n = 0;
    repeat(20) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(100) @(posedge clk) ;

    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end





endmodule
